The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal or by enlarging or constricting the conducting channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor.
The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET appears to the left of FIG. 1.
A thin dielectric layer is disposed on the substrate above the channel, and a “gate” structure (G) is disposed over the dielectric layer, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.)
Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded or biased at a desired voltage depending on applications.
Generally, when there is no voltage applied to the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity, plus or minus) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors are used, often paired with one another.
While particular n- and p-type dopants are described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopants).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
Decoupling Capacitors
Capacitors which are used for decoupling noise out of power supplies are called “decaps”. When a decap is incorporated into an integrated circuit (IC) chip, it can consume significant, valuable chip area. One solution is using deep trench (DT) caps for decoupling applications. DT caps have extremely high capacitance/area density, but also suffer from high equivalent series resistance (ESR).
FIG. 2A illustrates a DT cap, formed in a bottle-neck trench, in a substrate. The trench is filled with polysilicon (“poly”, doped to be conductive, herein referred to as “DT Poly”), is lined with a dielectric insulator, and a buried plate (conductive) is formed surrounding the trench by implantation or doping. The substrate may be a SOI-type substrate, having a silicon layer (not shown) over a buried oxide (BOX) layer. Such DT capacitors are commonly used in conjunction with an access device (FET transistor) to form a DRAM cell. The deep trench (DT) has a depth “D” and a width “W”.
For decoupling applications, high frequency response of the capacitor is paramount. The high ESR of the DT capacitor means that high frequency performance can be compromised. Typical planar MOS capacitors do not suffer as much from ESR effects, but have low density.
Therefore, and as illustrated by the following prior art, a need exists for a capacitor with higher capacitance per area than planar MOS caps, but with reduced ESR compared to DT caps.
FIG. 2B illustrates a planar (or “flat”) MOS cap. This capacitor is formed in a manner similar (substantially identical) to that of a FET, except that the source/drain implantations are of the same polarity as the cell well, and therefore no channel is formed. For example, in a p-type substrate, an n-well is formed. A gate stack comprising a dielectric on the substrate and a conductive (such as poly) structure (electrode) on the dielectric is disposed on the substrate, above the n-well. Source/drain implants are performed, in this case, “n+”, the same polarity as the cell well. For a FET, such as shown in FIG. 1, the source/drain implants have opposite polarity from the well, so that a channel is formed. In FIG. 2B, shallow trench isolation (STI) is shown surrounding (and isolating) the capacitor structure, in much the same manner as STI is used to isolate FETs from one another.
Related Patents
U.S. Pat. No. 6,121,106 (IBM, 2000), incorporated by reference herein, discloses a method for forming an integrated trench capacitor. A shallow trench capacitor is disclosed that is fabricated by forming a shallow trench in a substrate extending below a surface of the substrate. A dielectric layer having a preselected thickness is grown in the shallow trench, and a polysilicon layer is deposited over the dielectric layer. The polysilicon layer is then planarized down to the nitride or pad layer forming a capacitor. By utilizing a non-critical mask to open up selected regions, isolation structures may then be formed through shallow trench technology.
U.S. Pat. No. 7,087,486 (IBM, 2006), incorporated by reference herein, discloses method for scalable, low-cost polysilicon capacitor in a planar DRAM. Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole. This patent is a division of U.S. Pat. No. 6,815,751.
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®).
When glossary terms (such as abbreviations) are used in the description, no distinction should be made between the use of capital (uppercase) and lowercase letters. For example “ABC”, “abc” and “Abc”, or any other combination of upper and lower case letters with these 3 letters in the same order, should be considered to have the same meaning as one another, unless indicated or explicitly stated to be otherwise. The same commonality generally applies to glossary terms (such as abbreviations) which include subscripts, which may appear with or without subscripts, such as “Xyz” and “Xyz”. Additionally, plurals of glossary terms may or may not include an apostrophe before the final “s”—for example, ABCs or ABC's.    cell well The cell well (sometimes abbreviated “CW”) is an area in the silicon substrate that is prepared for functioning as a transistor or memory cell device by doping with an electron acceptor material such as boron or indium (p, electron acceptors or holes) or with an electron donor material such as phosphorous or arsenic (n, electron donors). The depth of a cell well is defined by the depth of the dopant distribution. Usually, the cell well is a big well area for many transistors. Usually, many NFETs will be disposed in one p-well and many PFETs will be disposed in one n-well.    CMP short for chemical-mechanical polishing. CMP is a process, using both chemicals and abrasives, comparable to lapping (analogous to sanding), for removing material from a built up structure. For example, after depositing and etching a number of elements, the top surface of the resulting structure may very uneven, needing to be smoothed (or leveled) out, prior to performing a subsequent process step. Generally, CMP will level out the high spots, leaving a relatively smooth planar surface.    deposition Deposition generally refers to the process of applying a material over another material (or the substrate). Chemical vapor deposition (CVD) is a common technique for depositing materials. Other “deposition” techniques, such as for applying resist or glass, may include “spin-on”, which generally involves providing a stream of material to the substrate, while the substrate is spinning, resulting in a relatively thin, flat, evenly-distributed coating of the material on the underlying substrate.    dopant element introduced into semiconductor to establish either p-type (acceptors) or n-type (donors) conductivity; common dopants in silicon: for p-type—boron (B), Indium (In); for n-type—phosphorous (P) arsenic (As), antimony (Sb). Dopants are of two types—“donors” and “acceptors”. N type implants are donors and P type are acceptors.    DRAM short for dynamic random access memory. DRAM is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Like SRAM, it is in the class of volatile memory devices, since it loses its data when the power supply is removed.     crystal, the deposited film takes on a lattice structure and orientation identical to those of the substrate. This is different from other thin-film deposition methods which deposit polycrystalline or amorphous films, even on single-crystal substrates. If a film is deposited on a substrate of the same composition, the process is called homoepitaxy; otherwise it is called heteroepitaxy.    ESR short for equivalent series resistance (sometimes referred to as “electrical series resistance”). In contrast with resistance, per se, ESR is an effective resistance that is used to describe the resistive parts of the impedance of certain electrical components. For example, the theoretical treatment of devices such as capacitors and inductors tends to assume they are ideal or “perfect” devices, contributing only capacitance or inductance to the circuit. However, all physical devices are constructed of materials with finite electrical resistance, which means that physical components contain some resistance in addition to their other properties.    FET short for field effect transistor. The FET is a transistor that relies on an electric field to control the shape and hence the conductivity of a “channel” in a semiconductor material. FETs are sometimes used as voltage-controlled resistors. The terminals of FETs are designated source (S), drain (D) and gate (G). Corresponding voltages applied to these terminals may be referred to as Vs, Vd, Vg, respectively. Substrate voltage may also play a role in FET operation.    ILD short for inter-level (or inter-layer) dielectric. Generally, ILD is a relatively thick layer of oxide deposited on completed underlying structures (such as FETs), which will support a layer(s) of metal lines interconnecting the various underlying structures. Holes may be etched through the ILD and filled with metal to make contact with elements (such as source, drain, gate) of the underlying structures.    lithography In lithography (or “photolithography”), a radiation sensitive “resist” coating is formed over one or more layers which are to be treated in some manner, such as to be selectively doped and/or to have a pattern transferred thereto. The resist, which is sometimes referred to as a photoresist, is itself first patterned by exposing it to radiation, where the radiation (selectively) passes through an intervening mask or template containing the pattern. As a result, the exposed or unexposed areas of the resist coating become more or less soluble, depending on the type of photoresist used. A developer is then used to remove the more soluble areas of the resist leaving a patterned resist. The pattered resist can then serve as a mask for the underlying layers which can then be selectively treated, such as to receive dopants and/or to undergo etching, for example.    MOSFET short for metal oxide semiconductor field-effect transistor. MOSFET is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material, and is accordingly called an NMOSFET or a PMOSFET. (The ‘metal’ in the name is an anachronism from early chips where gates were metal; modern chips use polysilicon gates, but are still called MOSFETs).    nitride commonly used to refer to silicon nitride (chemical formula Si3N4). A dielectric material commonly used in integrated circuit manufacturing. Forms an excellent mask (barrier) against oxidation of silicon (Si). Nitride is commonly used as a hard mask (HM).    oxide commonly used to refer to silicon dioxide (SiO2). Also known as silica. SiO2 is the most common insulator in semiconductor device technology, particularly in silicon MOS/CMOS where it is used as a gate dielectric (gate oxide); high quality films are obtained by thermal oxidation of silicon. Thermal SiO2 forms a smooth, low-defect interface with Si, and can be also readily deposited by CVD. Oxide may also be used to fill STI trenches, form spacer structures, and as an inter-level dielectric, for example.    poly short for polycrystalline silicon (Si). Heavily doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices.    p-type semiconductor in which concentration of “holes” is higher than the concentration of electrons. See n-type. Examples of p-type silicon include silicon doped (enhanced) with boron (B), Indium (In) and the like.    resist short for photoresist. also abbreviated “PR”. Photoresist is often used as a masking material in photolithographic processes to reproduce either a positive or a negative image on a structure, prior to etching (removal of material which is not masked). PR is usually washed off after having served its purpose as a masking material.    spacer a spacer, as the name implies, is a material (such as a layer of oxide) disposed on an element (such as a poly gate electrode). For example, sidewall spacers disposed on opposite sides of a gate electrode structure cause subsequent implants to occur further away from the gate than otherwise (without the spacers in place), thereby controlling (increasing) the length of a channel under the gate electrode structure.    STI short for shallow trench isolation. Generally, a trench etched into the substrate and filled with an insulating material such as oxide, to isolate one region of the substrate from an adjacent region of the substrate. One or more transistors of a given polarity may be disposed within an area isolated by STI.